/tech/ - Technology★

>>816022 (OP)

So far all we got are some SOCs

https://www.sifive.com/products/risc-v-core-ip/

http://www.lowrisc.org/

Lowrisc is running along.

E300 chipset is a success.

U500 has been announced, I will definitely be getting it for my router and low powered server.

Nvidia uses it amongst their 6 gorrilion arcitectures on their GPU's if that means anything.

>>816031

How cheap are those and are they entierly blob free?

>>816051

>Nvidia uses it amongst their 6 gorrilion arcitectures on their GPU's if that means anything.

U wot? What role does it play?

>>816062

Ask the designers of nvidia gpu's after the GTX 900 series or the nouveau devs. I have no fucking clue myself.

>>816051

Pricing isn't avaliable yet.

The only hardware we have is the HiFive1, an arduino alternative, at $59.

They are blob free and the U500(linux capable) will also be blob free.

>>816062

>>816065

They're replacing their proprietary RISC architecture called Falcon.

Currently they're just controller chips but the hope iirc is so they can balance out their licencing issues and reduce the amount of different architectures.

>>816067

Tell me if nvida ever removes the shitty hash signature check from their newer chips and that would be awesome with nouveau. Otherwise the U500 sounds very nice for a openbsd powered router. I am curious though, I wonder how (((they))) will ruin or backdoor RISC-V? Like I realize at the hardware level they are fucked by side-channels. But usually (((they))) stick a easy access backdoor like a (((debugger))) into such things. Surely (((they))) did so to these too. Otherwise it will just remain a niche arcitecture for buisnesses and autists looking for low powered non backdoored chips. Maybe intel will stick it in their newer x86 chips as a ME chip or something like that.

>>816022 (OP)

RISC is gradually learning Intel did nothing wrong. Example: they realized unaligned access is good and now allow it in RISC-V.

>>816084

RISCV is built with extensions in mind, Nvidia simply made the extensions they needed, which is called NV-RISCV.

RISC-V as a foundation doesn't create micro-architecture which would create the backdoors you propose.

Nvidia can quite happily create their own chips and sifive(U500) can make theirs.

I can't remember properly because the video I watched was years ago but the foundation is the one who allows your product to be called RISCV compliant or not, so if a vendor creates some bizarre backdoor version of the spec they aren't legally allowed to call it RISCV.

>>816117

What if the (((debugging))) extensions are the backdoors?

>>816118

Shit man, until we can look at each chip with a microscope you will have to have some level of trust, all instructions documented along with open source firmware is pretty good,

https://github.com/riscv/riscv-debug-spec

Find a backdoor.

>>816119

It's true. The industry realized it's a good thing and can be made zero cost like in recent i7s. So RISC-V explicitly allows it now so they can do similar optimization since the compiler can't always know at runtime.

All those years of RISCfags telling us how everyone else was wrong on unaligned access and yet here we are.

>>816129

>zero cost

>unaligned access

How is this accomplished? I thought by definition there is energy expenditure for such?

>>816130

Dunno, but the wizards at Intel figured it out.

>>816140

>you need to know how to build an i7 from sand to comment

Zero cost unaligned accesses sure do piss off the RISC fanbois.

>>816031

lol, lowrisc is vapourware. Don't list it as a SoC that "we got".

>When can I buy a lowRISC SoC?

>As with most tech projects, the most accurate answer is “When it’s ready”.

>We are expecting to crowdfund an initial instantiation of the lowRISC platform during the course of 2017.

It said "2016" last year. They've got ~7 weeks before they need to change their FAQ to read "2018".

http://www.lowrisc.org/faq/